Intel x86 processor processor interrupt handling overview knowledge points

Processor interrupt handling is a must-have knowledge for learning computer architecture. Under Intel's x86 processors, interrupts are collectively referred to as external interrupts, exceptions, and traps.
  • External interrupts come from hardware and are random.
  • An exception originates from within the processor and indicates that some error condition has been detected during the execution of an instruction by the processor.
  • Traps come from programs and are generated by instructions such as INT n, INTO, etc.
External interrupts can be masked, but lines and exceptions cannot be masked. The way to mask the interrupt is to clear the IF flag in the EFLAGS register.
  • A program that handles an interrupt is called an interrupt handler.
  • Programs that handle exceptions are called exception handlers.
  • The program that handles the trap is called a system call service program.
Handlers can be located anywhere in the space and can have different privilege levels. Intel processors call handler entries gates. The available gates are divided into interrupt gates, trap gates and task gates. Interrupt gates and trap gates are the gateways into the exception handler, and are defined by the descriptors of the interrupt gate and trap gate, respectively. The selector and offset together define the entry address of a handler. The IF flag is cleared when the interrupt gate enters the handler, while the IF flag remains unchanged when the trap gate enters the handler.
The Intel processor assigns an interrupt vector number to each of its interrupts and exceptions, and defines an interrupt descriptor table (IDT) to establish the corresponding relationship between the interrupt vector number and the gate. There are a total of 256 interrupt vector numbers defined by the Intel processor, of which 0~31 are reserved by the processor. An IDT can reside anywhere in the linear address space. Intel processors specifically provide an IDTR register to record the base address and limit information of the IDT. Fault class exceptions are correctable. Termination exceptions are serious errors, and the processor cannot guarantee that the program will continue to execute normally.
Intel stipulates that control can only be transferred to the code segment of the same level or higher privilege level through the interrupt gate or trap gate. Usually, the handler is defined in the kernel code segment (0 privilege level code segment).
The interrupt or exception handler can also be entered by trapping the instruction, which requires that the privilege level (CPL) before entering must be less than or equal to the privilege level (DPL) of the gate descriptor. User programs generally cannot enter interrupt handlers through the INT n instruction.
If the processor is at the 0th privilege level when the interrupt or exception occurs, the handler can directly use the system stack of the current process without switching the stack. If it happens at privilege level 3, you need to switch the stack.
When an interrupt occurs, the processor will automatically push some parameters on the top of the stack, where EFLAGS is the system state before the interrupt or exception occurs, SS:ESP is the top of the user stack before the interrupt or exception occurs, and CS:EIP is the interrupt or exception. 's return address. SS:ESP is pushed on top of the stack only when the stack switches.
In 64-bit mode, the handler must be in the 64-bit code segment, so the interrupt and trap gate descriptors are extended to 16 bytes, and the offset is extended to 64 bits; IDT finds the gate descriptor that only has the new format ; The stack width has become 64 bits, and when an interrupt occurs, it will unconditionally push the stack pointer (SS:RSP). When the stack needs to be switched, SS is forcibly set to NULL; the interrupt stack table (IST) mechanism has been added. Allows specific interrupts or exceptions to specify a dedicated stack.
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