Extended Concepts of Memory Management

  • Flat-panel memory management. Block out the segment management, completely adopt the page management. The practice is to define a code segment and define a data segment. Both the code segment and the data segment are 4GB in size. The logical address is thus a linear address.
  • Secure tablet-style memory management. The practice is to define the kernel code segment, the kernel data segment, the user code segment, and the user data segment. The base addresses of the four segments are all 0 and the size is 4GB. The kernel segment is used when the process executes the kernel code, and the user segment is used when the user code is executed. Segment address translation is masked, but privilege-based protection features are preserved. For the same process, since its use of the four segments will never overlap, the four segments can be superimposed and regarded as the process flat address space, and the four sets of page directories/page tables can also be merged into one set. After merging, page table entries may represent pages in different segments. The U/S flag of the page table entry is used to distinguish user pages from kernel pages. If the operating system kernel can ensure that there are no overlapping entries in the page directory/page table, the mutual isolation between processes can be guaranteed.
  • Multi-segment memory management. That is, segment management is completely adopted, and page management is shielded.
  • Page-based memory management based on physical address expansion. Later IA-32 systems introduced the Physical Address Extension (PAE) mechanism to support 36-bit physical addresses. In this management mode, the physical address space is expanded to 64GB, but the linear address space is still 4GB. Page directory and page table entries are extended to 64 bits, so the number of entries in a page directory or page table becomes 512, and a page directory can only describe a 1GB linear address space. So a page directory pointer table (PDP) with only four entries is introduced. CR3 points to the PDP. The address translation mechanism is modified. When the PS bit in the page directory entry is set to 1, the page it describes becomes a 2MB page.
  • 64-bit tablet memory management. In 64-bit mode, segments are normally closed and segment bounds checks are no longer done. The base address processors of CS, DS, ES, and SS are all regarded as 0. However, FS and GS may not be 0, and the base address of FS or GS should be added when converting the logical address to the look-ahead address. The base address of FS and GS is a 64-bit address, and only its lower 32 bits are used in compatibility mode, which is recorded in MSR.
In 64-bit mode, the management of memory relies entirely on the paging mechanism. The Intel64 architecture extends the PAE mechanism to support 64-bit linear addresses and 52-bit physical addresses. Extensions include:
  1. The page directory pointer table has been expanded to 512 entries.
  2. A fourth-level page mapping table PML4 is introduced, each entry of which can point to a PDP.
  3. All four-level page table entries are extended to 64 bits.
  4. The PS flag in the page directory entry is used to control 4KB and 2MB pages.
  5. All page table entries have a new execution prohibition flag EXB on the 63rd bit.
zh_CNZH-CN