Summary of paged memory management

In segment-paged memory management, the linear address of a segment is divided into linear pages of equal size (4KB, 4MB, or 2MB, etc.).The physical memory space is also divided into physical pages of the same size. The operating system maintains a page table that manages the mapping of linear pages to physical pages. Page tables are divided into two levels in the IA-32 architecture, namely page directories and page tables
The page directory is an array whose elements are called page directory entries (PDEs), and each page directory entry describes a page table. The size of the page directory is one page (4KB), and there are 1024 page directory entries in a page directory. The size of a page directory entry is 4 bytes.The page table size is one page (4KB).Page table entries are 4 bytes in size, so a page table can describe up to 1024 linear pages.
Physical pages are pre-divided and must start on a 4KB (2^12) boundary. So the lower 12 bits are all zeros. Then the lower 12 bits can store additional information.
P is the presence bit. R/W is the read and write flag. U/S is the user flag, 0 means super user. A is the access flag. D is the dirty flag.
In the page directory entry, the PAT flag is replaced by the PS flag, indicating the physical page size.
The CR3 register specifically stores the physical address of the currently used page directory, so CR3 is also called the page directory base address register. As long as the process is alive, its page directory should remain in memory.
Page directory entries can also directly point to physical pages to speed up address translation. Usually, the page occupied by the operating system kernel is set to a 4MB page. The PS address of the page directory entry is 1, which describes a 4MB page rather than a page table.
The page management mechanism is started by the operating system kernel, and the startup method is to set the PG flag in CR0 to 1.
After the paging mechanism is activated, each linear address needs to be translated from the page directory and the page table. The IA-32 architecture incorporates a cache TIB that stores recently used page directory and page table entries. The frequent refresh of TIBs is the responsibility of the operating system kernel. When page directory and page table entries change, the kernel must invalidate the corresponding entries in the TIB. When CR3 is changed, all content in the TIB (except the Global page) is automatically invalidated. The INVLPG instruction can invalidate the specified entry in the TLB.