Summary of Segment Memory Management

The IA-32 system provides a segmented page memory management mechanism, which is segmented and then paged. Paging is provided to support virtual memory.
  • part: The addressable linear memory space of the processor is divided into several segments of different sizes. A segment is a contiguous extent in linear address space. Sections can hold code, data, stacks, or other data structures. The attribute information of the segment is described by the corresponding segment descriptor. A segment descriptor is a data structure. Intel uses segment descriptor table to manage. The segment descriptor table can be up to 64KB.
    • When G is 0, the segment is in bytes, and the maximum segment length is 1MB. When G is 1, segments are measured in pages (4kb). The maximum segment size is 4GB.
    • DPL is the privilege level of the segment, and its value is between 0 and 3.
    • S is a system flag that distinguishes the category of the segment. 0 means system segment, 1 means user segment.
    • Type is the type of the segment:
      • for the system segment. The type field consists of 4 bits and can represent one of 16 system segment types.
      • for the user segment.
        • The third bit is 0 to indicate the data segment, the second bit indicates the expansion direction of the address (0 indicates the large expansion direction), and the first bit indicates whether the segment is writable.
        • The third bit is 1 for the code segment, and the second bit is the compatibility flag (0 for non-compliant). The first bit is the readable bit.
        • Bit 0 is the access bit. 0 means the segment has not been accessed.
    • The D/B flag indicates the effective address and operand length.
    • The L flag appears only in code segments in IA-32e mode. 1 for 64-bit mode
    • A stack segment is usually a downward-extending, readable and writable data segment.
  • Segment descriptor table:
    • Global Descriptor Table (GDT). A GDT must be defined for the system before it can enter protected mode. The IA-32 architecture specifically defines a GDTR register to store the current GDT information.
    • The local descriptor table (LDT) is a system segment in which local descriptors, such as the process's own code segment, data segment, etc., can be stored. The IA-32 system specifically provides an LDTR register for saving the currently used LDT information.
        A segment descriptor can be identified by its index in the segment descriptor table, which is called a segment selector. A segment selector is a 16-bit identifier. The second bit is the indicator (TI) indicating the descriptor table to which the index is paired (0 for GDT). Bits 3-15 indicate the index, the calibration position. Bits 0 and 1 are the request privilege level RPL.A segment selector plus an offset can uniquely identify a logical address.A logical address is an address used by a program, not a linear address, nor a physical address.
The IA-32 architecture provides six segment registers, namely CS, SS, DS, ES, FS and GS. Each segment register can buffer a segment descriptor.
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